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RF SIGNAL PROCESSOR
S5L1462B
INTRODUCTION
80-QFP-1420C The S5L1462B01 is used for CD and DVD playback. It receives optical signal from the optical pick-up to produce the data-generating RF signal, the servo error signal for stable servo control, and the monitor signal. This RF IC can be used in the CD 1x, 2x, or the DVD 1x CLV (Constant Linear Velocity) mode. The DVD mode is compatible with the Single/Dual Layer disc. The CD mode is compatible with the CD-ROM, CD-R and CD-RW disc.
FEATURES
* * * * * * * * * * * * * * * * * * Can be used with CD 1x, 2x, and DVD 1x playback mode. Able to input and handle all optical signal of the CD-R's P/U. Built-in pre-amp with adjustable gain, compatible with various P/U. Built-in AGC (Automatic Gain Control) circuit operated by light detection feedback. Built-in RF AMP & Equalizer compatible with CD 1x, 2x, and DVD 1x. Built-in Astigmatism Method FE (Focus Error) AMP for CD and DVD use. Built-in 3-BEAM TE (Tracking Error) AMP for CD. Built-in 1-BEAM DPD (Differential Phase Detector) TE AMP for DVD. Built-in RF mirror detection circuit for CD and DVD. Built-in RF defect detection circuit for CD and DVD. Built-in FOK (Focus O.K.) signal detection circuit for CD and DVD. Built-in RF envelope signal generating circuit for CD and DVD. Built-in interrupt defect detection circuit. Built-in ALPC (Automatic Laser Power Control) circuit for CD and DVD. Built-in standard voltage generating circuit for analog circuit use (2.5V, 1.65V). Built-in defective waveform detection circuit. Power operating range: 4.5 - 5.5 V, 3.0 - 3.6 V. 80 PIN, QFP.
ORDERING INFORMATION
Device S5L1462B01-Q0R0 Package 80-QFP-1420C Temperature Range -25 to +70C
1
S5L1462B
RF SIGNAL PROCESSOR
BLOCK DIAGRAM
RFAGCO
AGC1IN
VZ0CTL
AGCBO
EOGND
EQVCC
RFEQO
AGC1C
AGC10
PLLGF
AGCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
to RF EQ AGC_DET tuning block PD_POL RFSUM_SEL
RFSUM ADVD BDVD DDVD 1 2 3 4
65
MIRRI
AGCP
AGCB
RDPF
EQIN
MUX6
RF Equalizer
AGCI
RFRP
64 63 62 61 60 59 58
CP1 CB1 RFRP CP2 Cpeak RFCT RESET STB CLOCK DATA
PDLIMITERS
RREFBF RREFEQ RREF
6 7 8
VREF
EQ_FREQ. RFSUM $ RF EQ_BOOST RFCT & AGC AMP MUX PLLCTL PD_LIMIT SW_CON MIRR GAIN_RFUM SW_CON1 TBAL DPDMUTE TE10FST AGC_HOLD Cpeak GAIN_TE1 AGC_LVL Phase DPDEQ1 VCPS LPS detector TE1 Front MUX
GCA EQ COM PDLIMITRES FAULT Defective waveform OUT detection circuit PLLCTL FLT_CTL HOLD_CTL
S/IF Block
57 56 55 54
GCA
EQ
COM
DPD VC AMP
53 52 51 50
VREFDPD DPDGND TE1RES PLLCTL FAULTOUT DPDEQ2 DPDEQ1 MIRR DPDVCC INTER0 INTER1
VREFEQ
9
EQ VC AMP A+C B+D
ADVD1 BDVD1 CDVD1 DDVD1 AVCC
10 11 12 13 14
GAIN_ABCD DPDEQ2 ABCDOFST + GCA -
to DPD Block
49 48 47
VREFA1 GAIN_FE VREFA
+
46
VREFAOF
Interruption Detect
45 44
VREFA
15
ANALOG FEOFST VC AMP
GCA
+ + GAIN_TE3 TFOFST TE38 TE MUX LPF
10dB
VREFA TE_ SEL
MUX INT_ONB
43
E F
16 17
GAIN_FE FEOFST ALPC LPF
10dB
INTER_TH
VBGRO LD0DVD PDDVD LD0CD PDCD AGND FE
18 19 20 21 22 23 24
FOK_TH DFCTTH1
DFCTTH2
42 41 PLLDFT DFCT1
ENVELOPE
FOK
DEFECT
ALPC_SEL
INTER Detect
INTER_ONB
25 26
ANALOG VC1 AMP
27
28
29
30
31
32 33
34
35
36
37
38 39 CC1 CC2
ENVB ENV
ENVP
VREFA1
AVCC1
ABCDI
DFCT_CP1
2
DFCT_CP2
INTERB
DVCC
ABCD
TE
GND
FOKB
40
RF SIGNAL PROCESSOR
S5L1462B
PIN DESCRIPTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Name RFSUM ADVD BDVD CDVD DDVD RREFBF RREFEQ RREF VREFEQ ADVD1 BDVD1 CDVD1 DDVD1 AVCC VREFA E F VBGRO LDODVD PDDVD LDOCD PDCD AGND FE INTERB TE AVCC1 VREFA1 ABCD ABCDI I/O I I I I I O I I I I P Description RF optical's main beam RFSUM AC Coupling input pin RF optical's main beam A AC Coupling input pin RF optical's main beam B AC Coupling input pin RF optical's
main beam
Related Blocks PRE AMP PRE AMP PRE AMP PRE AMP PRE AMP RF AMP RF EQ ANALOG EQ VC AMP SERVO AMP SERVO AMP SERVO AMP SERVO AMP ANALOG ANA VC AMP TE 3B TE 3B ALPC ALPC ALPC ALPC ALPC ANALOG FE AMP INTERRUPTION TE AMP ANALOG ANA VC1 AMP ABCD AMP SERVO MONIT
Related Parts P/U P/U P/U P/U P/U P/U P/U P/U P/U SERVO P/U P/U P/U P/U P/U P/U DSSP SERVO DSSP -
C AC Coupling input pin
RF optical's main beam D AC Coupling input pin RF AMP I/O Buffer Bias resistance connection pin RF EQ Bias resistance connection pin ANALOG Block Bias resistance connection pin RF EQ Center voltage CAP connection pin SERVO optical's main beam A input pin SERVO optical's main beam B input pin SERVO optical's main beam C input pin SERVO optical's main beam D input pin ANALOG Part power voltage (5 V) input pin
-/O ANALOG Part Center voltage CAP connection pin. Uses another block. I I SERVO CD optical's sub beam E input pin SERVO CD optical's sub beam F input pin
I/O ALPC Bandgap voltage input and bandgap output pin O I O I P O O O P DVD optical's Laser Diode operating voltage output pin DVD optical's Laser Monitor Diode voltage input pin CD optical Laser Diode operating voltage output pin CD optical Laser Monitor Diode voltage input pin ANALOG Part power GND pin FE AMP output pin Interruption button detection time constant cap. connection TE AMP output pin ANALOG Part power voltage (3.3 V) input pin
-/O ANALOG Part Center voltage1 (1.65 V) CAP connection pin O I ABCD AMP output pin SERVO MONITOR ABCD AC Coupling input pin
3
S5L1462B
RF SIGNAL PROCESSOR
PIN DESCRIPTION (Continued)
No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Name ENVP ENVB ENV DGND FOKB DFCT_CP1 DFCT_CP2 CC1 CC2 DVCC DFCT1 PLLDFT INTERO INTERI DPDVCC MIRR DPDEQ1 DPDEQ2 FAULTOUT PLLCTL TE1RES DPDGND VREFDPD I/O O P O O I P O O O I P O O O O I I P O I I I I O Description RF ENVELOPE detecting Peak Hold time constant selection RC connection pin RF ENVELOPE detecting Bottom Hold time constant selection RC connection pin RF ENVELOPE Detect output pin DIGITAL Circuit power GND input pin FOCUS OK Comparator output pin (L: FOCUS OK) SERVO DEFECT maximum time selection Peak Hold time constant connection pin PLL DEFECT minimum time selection Peak Hold time constant connection pin DEFECT peak detector circuit output pin DEFECT AC Coupling input pin DIGITAL circuit power voltage (5 V) input pin SERVO DEFECT output pin PLL DEFECT output pin INTERRUPT Defect Detection output pin INTERRUPT Defect Detection input pin DPD TE power voltage (5V) input pin MIRROR output pin DPD EQ (A+C) output pin DPD EQ (B+D) output pin DPD abnormal waveform output pin (MONITOR) DPD TE PLL variable input pin DPD TE PLL variable bias resistance DPD TE power GND input pin DPD TE CENTER voltage CAP connection pin PDLIMITK BIAS resistance connection pin DATA input pin CLOCK input pin DATA ENABLE input pin Serial Register Reset pin MIRROR RF RIPPLE CENTER voltage output pin AGC/AGC1 peaking protection SW control voltage input pin Related Blocks RF ENV RF ENV RF ENV DIGITAL FOKB DFCT DFCT DFCT DFCT DIGITAL DEFECT DEFECT INTERRUPT INTERRUPT DPD MIRR DPD DPD DPD DPD DPD DPD DPD VC AMP DPD
Serial Interface Serial Interface Serial Interface Serial Interface
Related Parts DSSP DSSP DSSP PLL DSSP SERVO MICOM MICOM MICOM MICOM DSSP -
54 PDLIMITRES 55 56 57 58 59 60 DATA CLOCK STB RESET RFCT Cpeak
MIRROR AGC/AGC1
4
RF SIGNAL PROCESSOR
S5L1462B
PIN DESCRIPTION (Continued)
No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name CP2 RFRP CB1 CP1 MIRRI EQVCC AGC1O AGC1C AGC1IN RFEQ0 EQIN RFAGCO AGCC EQGND AGCBO AGCB AGCP RDPF VZOCTL PLLGF I/O O I P O I O I O P I I Description RFCT generating PEAK HOLD time constant RC connection pin MIRROR RF RIPPLE AMP output pin RFRP generating BOTTOM HOLD time constant RC connection pin RFRP generating PEAK HOLD time constant RC connection pin MIRR signal generating input pin RF EQ power voltage input pin RF AGC1 AMP output pin AGC1 time constant CAP connection pin RF AGC1 AMP input pin RF EQ output pin RF EQ RFAGCO input pin RF AGC AMP output pin AGC time constant CAP connection pin RF EQ power GND input pin RF EQ BIAS resistance connection pin RF AGC RF BOTTOM HOLD time constant RC connection pin RF AGC RF PEAK HOLD time constant RC connection pin RF EQ FREQUENCY selection BIAS resistance connection pin RF EQ zero control voltage Wide range PLL RF EQ BOOST, PEAK FREQUENCY GAIN control pin (internally designed PLLG, PLLF resistance) Related Blocks MIRROR MIRROR MIRROR MIRROR MIRROR RF EQ RF AGC1 RF AGC1 RF AGC1 RF EQ RFEQ RFENV RF AGC RF AGC RF EQ RF EQ RF AGC RF AGC RF EQ RF EQ RF EQ Related Parts DSSP PLL DSSP DSSP DSSP
5
S5L1462B
RF SIGNAL PROCESSOR
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Item Power Voltage Operating Temperature Power Expenditure Storage Temperature Symbol Vs Temp PD Tstg Standard Value 6 -25 to +70 1100 -40 to +125 Unit V C mW C Notes
Item
Symbol MIN
Standard Value TYP 5 120 MAX 5.25 160
Unit
Notes
Power Voltage Operating Current
Vo Ic
4.75 -
V mA
6
RF SIGNAL PROCESSOR
S5L1462B
ELECTRICAL CHARACTERISTICS
(V CC = 5V, VCC1 = 3.3V, GND = 0V, Vc = 2.5V, Vc1 = 1.65V Ta = 25C, VC is center of standard output voltage.) No Item Symbol Input Measuring point Output Typ. Max.
100 120 140 120 140 160
Unit
Min.
80 100 120
CIRCUIT CURRENT 1 2 3 Supply current Supply current Supply current IccL IccT IccH vdd=4.5V,TE1 BLOCK operation vdd=5V,TE1 BLOCK operation vdd=5.5V,TE1 BLOCK operation mA mA mA
RF SUM & AGC AMP 4 Vrfsum1 RFSUM=1MHz, 1.5Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, DVD Mode RFSUM=1MHz, 1Vpp,RFSUM_SEL=0 GAIN_RFSUM=0dB, DVD Mode RFSUM=1MHz, 0.1Vpp, RFSUM_SEL=0 GAIN_RFSUM=20dB, CD Mode (A-D)DVD=1MHz, 0.25Vpp, RFSUM_SEL=1 GAIN_RFSUM=0dB, DVD Mode RFSUM=Freq. Sweep, 1.0Vpp, RFSUM_SEL=0, GAIN_RFSUM=0dB,DVD Mode RFSUM=Freq. Sweep, 0.1Vpp, RFSUM_SEL=0, GAIN_RFSUM=20dB,CD Mode RFSUM=1MHz, 2Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, DVD Mode RFSUM=1MHz, 0.5Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, DVD Mode RFSUM=1MHz, 1Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, AGC_LVL=00H, DVD Mode RFSUM=1MHz, 1Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, AGC_LVL=10H, DVD Mode RFSUM=1MHz, 1Vpp, RFSUM_SEL=0 GAIN_RFSUM=0dB, AGC_LVL=11H, DVD Mode RFAGCO (AGCHOLD= L) 0.3 0.5 0.7 10 MHz RFAGCO (AGC_LVL=0 1H,) 0.8 1 1.2 Vpp
5
RF Sum Amp Voltage Gain
Vrfsum2
6
Vrfsum3
7
Vrfsum4
8
RF Sum Amp Unit Gain Bandwidth
Frfsum1
9
Frfsum2
5
-
-
10
AGC Voltage Gain
Gagc1
0.8
1.0
1.2
Vpp
11
Gagc2
12
AGC AMP Out. LEVEL Adjust RANGE
Vagc1
13
Vagc2
0.55
0.75
0.95
Vpp
14
Vagc3
1.00
1.25
1.50
7
S5L1462B
RF SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
No
AGC1 15 AGC1 Out. Level AGC1 Out. Level 1 AGC1 Out. Level 2 Band Width (-3dB) AGC1 Normal Gain AGC1 Out. DC Vagc1 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD: 1, AGC1_LVL:01, AGC1_ON:0 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD:1, AGC1_LVL:00, AGC1_ON:0 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD: 1, AGC1_LVL:11, AGC1_ON:0 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD: 1, AGC1_LVL:01, AGC1_ON:0 AGC1IN:sin 0.5Vpp 5MHz dc 2.5V AGC1_HOLD: 1, AGC1_LVL:11, AGC1_ON:0 AGC1IN: dc 2.5V AGC1_HOLD: 1, AGC1_LVL:11, AGC1_ON:0 AGC10 0.8 1 1.2 Vpp
Item
Symbol
Input
Measuring point Min.
Output Typ. Max.
Unit
16
Vagc11
AGC10
0.6
0.75
0.9
Vpp
17
Vagc12
AGC10
1.15
1.45
1.75
Vpp
18
Fagc12
AGC10
6
-
-
MHz
19
Aagc1
AGC10
20
dB
20
Vdcagc1
AGC10
2.5
V
ABCD SUM AMP 21 ABCD SUM AMP voltage gain Vsum1 (A-D)DVD1=0.5MHz, 250mVpp+Vc, DVD Mode GAIN_ABCD:6dB (A-D)DVD1=200kHz, 20mVpp+Vc, CD Mode GAIN_ABCD:30dB (A-D)DVD1=Freq. Sweep,250mVpp+Vc, DVD Mode, GAIN_ABCD:6dB (A-D)DVD1= Freq. Sweep,125mVpp+Vc, CD Mode, GAIN_ABCD:12dB ABCD 500 kHz ABCD 1.8 2.0 2.2 Vpp
22 23 RF SUM AMP -3dB Gain Bandwidth
Vsum2 Fsum1
24
Fsum2
8
RF SIGNAL PROCESSOR
S5L1462B
Electrical Characteristics (Continued)
No Item Symbol Input Measuring point
RFEQO EQF=80H EQG=83H RFEQ0 EQF=80H EQG=83H RFEQO EQ_BOOST =0dB EQG_CEN =9dB EQ_FREQ =0% RFEQO EQF=80H 2
Min.
1.5
Output Typ. Max.
2.0 6.4 2.5 3 2.3
Unit
RF EQUALIZER 25 26 27 EQ Standard Output EQ Peak Frequency EQ Out DC Vrfeqdvd Fpeakdvd Veq_dc EQIN=100kHz, 1Vpp, EQIN= Freq. Sweep, 250mVpp EQIN=DC 2.5V Vpp MHz V
28
F1dvd
EQIN =0.4MHz, 250mVpp
-2
0
2
29 30 31 32 33 34 35 36
EQ Peak Frequency DVD
F2dvd F3dvd F4dvd
EQIN =3.54MHz, 250mVpp EQIN =6.4MHz, 250mVpp EQIN=12.8MHz,250mVpp EQIN=Freq. Sweep 250mVpp EQG=80H EQIN=Freq. Sweep 250mVpp EQG=81H EQIN=Freq. Sweep 250mVpp EQG=82H EQIN=Freq. Sweep 250mVpp EQG=83H RFSUM=0.1MHz, 250mVpp
4.0 7.0 -30 2 4 6 9
6.0 9.0 -10 4 6 8 11 0
8.0 11.0 0 6 8 10 13 +1
dB
Boost Gain Range DVD
Gbg1dvd Gbg2dvd Gbg3dvd Gbg4dvd F1cd
dB
RFEQO EQ_BOOST =0dB EQG_CEN =9dB EQ_FREQ =0%
-1
37 38 39 40 41 42 43
EQ peak frequency CD
F1cd F1cd F1cd
RFSUM=0.5MHz, 250mVpp RFSUM=0.72MHz, 250mVpp RFSUM=1.4MHz, 250mVpp EQIN=Freq Sweep 250mVpp EQG=80H EQIN=Freq Sweep 250mVpp EQG=81H EQIN=Freq Sweep 250mVpp EQG=82H EQIN=Freq Sweep 250mVpp EQG=83H
1.5 7.0 -30 3
3.5 9.0 -10 4 6 8 11
5.5 11.0 0 5 8 10 13
dB
Boost Gain Range cd
Gbg1cd Gbg2cd Gbg3cd Gbg4cd
RFEQO EQF=80H
4 6 9
dB
9
S5L1462B
RF SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
No Item Symbol Input Measuring point Min. Output Typ. Max. Unit
FOCUS ERROR AMP 44 Vfedvd1 (A,C)DVD1=1kHz Sine, 630mVpp+Vc (B,D)DVD1=1kHz Sine(I) 630mVpp+Vc GAIN_FE=-2dB, DVD Mode (A,C)DVD1=1kHz Sine 63mVpp+Vc (B,D)DVD1=1kHz Sine(I) 63mVpp+Vc GAIN_FE=18dB, DVD Mode (A,C)DVD1=1kHz Sine 200mVpp+Vc (B,D)DVD1=1kHz Sine(I) 200mVpp+Vc GAIN_FE=8dB, CD Mode (A,C)DVD1=1kHz Sine 40mVpp+Vc (B,D)DVD1=1kHz Sine(I) 40mVpp+Vc GAIN_FE=22dB, CD Mode (B,D)DVD1=Vc+0.7V, (A,C)DVD1=Vc, GAIN_FE=-2dB, DVD (B,D)DVD1=Vc-0.7V, (A,C)DVD1=Vc, GAIN_FE=-2dB, DVD (B,D)DVD1=Vc+0.7V, (A,C)DVD1=Vc, GAIN_FE=0dB, CD (B,D)DVD1=Vc-0.7V, (A,C)DVD1=Vc, GAIN_FE=0dB, CD (A,C)DVD1=Sine 63mVpp+Vc (B,D)DVD1=Sine(I) 63mVpp+Vc GAIN_FE=18dB, Freq. Sweep, DVD Mode (A,C)DVD1=Sine 63mVpp+Vc (B,D)DVD1=Sine(I) 63mVpp+Vc GAIN_FE=18dB,Freq. Sweep , CD Mode (A-D)DVD1=Vc, GAIN_FE=18dB,FEOFST=80H FE FE 25K FE 2.8 FE 2.8 2.9 V FE 1.8 2.0 2.2 Vpp
45
Voltage Gain
Vfedvd2
46
Vfecd1
47
Vfecd2
48
Output Voltage H Output Voltage L Output Voltage H Output Voltage L Bandwidth ( -3dB Freq.)
Vfehdvd
49
Vfeldvd
0.4
0.5
50
Vfehcd
2.9
V
51
Vfelcd
0.4
0.5
52
Ffedvd
35K
45K
Hz
53
Ffecd
25K
35K
45K
Hz
54
Offset Voltage
Vosfe
-300
0
300
mV
10
RF SIGNAL PROCESSOR
S5L1462B
ELECTRICAL CHARACTERISTICS (Continued)
No Item Symbol Input Measuring point Min.
1.8 DPDEQ1 DPDEQ2 4 8 11 dB
Output Typ. Max.
2.0 2.2
Unit
TRACKING ERROR AMP (1-BEAM) 55 56 57 DPD EQ Gain Characteristics Variable range DPD EQ Standard Gain Vdpdeq1 Vdpdeq2 Gdpdeqr (A-D)DVD= 500mVpp 200kHz Sine+Vc, GAIN_TE1 = 0dB (A-D)DVD= 45mVpp 200kHz Sine+Vc, GAIN_TE1 = 27dB Vpp
(A-D)DVD: 251mVpp Freq. Sweep (INT_ONB=1 Sine+Vc, GAIN_TE1 = 12dB FLT_CNT=1) (A-D)DVD: 251mVpp 5MHz Sine+Vc (A,C)DVD, (B,D) DVD's phase difference 0 GAIN_TE1 = 12dB (A-D)DVD: 251mVpp 5MHz Sine+Vc When (A,C)DVD's phase difference is 45 ahead of (B,D)DVD, GAIN_TE1 = 12dB (A-D)DVD: 251mVpp 5MHz Sine+Vc When (A,C)DVD's phase difference is 45 behind (B,D)DVD GAIN_TE1 = 12dB (A,C)DVD=251mVpp 2.616MHz Sine + Vc (B,D)DVD=251mVpp 2.616MHz Sine + Vc TBAL=00H, GAIN_TE1=12dB (A,C) DVD=251mVpp 2.616MHz Sine + vc (B,D) DVD=251mVpp 2.616MHz Sine + vc TBAL=FFH, Gain TE1=12dB (A,C)DVD=2MHz, 300mVpp, duty 50% Pulse (B,D)DVD signal with a phase 90 late PD_LIMIT=90ns (B,D)DVD=2MHz, 300mVpp, duty 50% Pulse (A,C)DVD signal with a phase 90 late PD_LIMIT=90ns (A,C)DVD=251mVpp,100kHz (B,D)DVD=251mVpp,2.616MHz Time measurement from Falling Edge with only (B,D)DVD, to when FAULTO becomes H (A,.B)DVD. (B.D) DVD =VC Gain_TE1=27dB TEOFST=80H (B,D)DVD FAULTO TE (INT_ONB=1 FLT_CNT=1) TE (INT_ONB=1 FLT_CNT=1) TE (INT_ONB=1 FLT_CNT=1)
58
Vph0
1.2
1.65
2.1
V
59
Output Voltage Correspond to Phase Difference
Vph1
0.05
0.65
1.05
V
60
Vph2
2.25
2.65
3.25
V
61
Tracking Balance Adjustment Range
Vbal1
0.33
V
62
Vbal2
2.97
63
Phase Comparator Limit
Vphlim1
2.55
3.25
V
64
Vphlim2
0.05
0.75
65
Abnormal Waveform Detection Circuit Offset Voltage
Tflt
450
900
ns
66
Voste1
TE (INT_ONB=1 FLT_CNT=1)
-300
0
300
mV
11
S5L1462B
RF SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
No Item Symbol Input Measuring point Min. Output Typ. Max. Unit
TRACKING ERROR AMP (3-BEARN) 67 TE3 Voltage Gain Vte31 E=1kHz Sine 316mVpp+Vc F=1kHz Sine(I) 316mVpp+Vc TBAL=80, GAIN_TE3=10dB, TEOFST=80H E=1kHz Sine 30mVpp+Vc, F=1kHz Sine(I) 30mVpp+Vc, TBAL=80, GAIN_TE3=30dB, TEOFST=80H E=Vc-0.7V,F= Vc,GAIN_FE=10dB E=Vc+0.7V,F=Vc,GAIN_FE=10dB E=Sine 316mVpp+Vc, Freq. Sweep F=Sine(I) 316mVpp+Vc, Freq. Sweep TBAL=80H, GAIN_TE3=10dB, TEOFST=80H E=1kHz Sine 316mVpp+Vc F=1kHz Sine(I) 316mVpp+Vc TBAL=00H, GAIN_TE3=18dB, TEOFST=80H E=1kHz Sine 316mVpp+Vc F=1kHz Sine(I) 316mVpp+Vc TBAL=FFH, GAIN_TE3=18dB, TEOFST=80H E,F=Vc,TBAL=80, GAIN_TE3 =26dB, TE3OFST=80H E,F=Vc, TBAL=80, Gain=TE3=26dB TEOFST=00H E,F=Vc, TBAL=80, Gain=TE3=26dB TEOFST=FFH TE TE TE 1.8 2.0 2.2 Vpp
68
Vte32
TE
69 70 71
Out. Voltage H Out. Voltage L Bandwidth (-3dB Freq.)
Vte3h Vte3l Fte3
TE TE TE
2.8
2.9 0.4 0.5 75K
V
45K
60K
Hz
72
Tracking Balance Range
Gte31
TE
3
-
-
dB
73
Gte32
-
-
-3
dB
74 75
Offset Voltage Tracking Offset Range
Voste3 Voste31
-300 0
0
300 0.5
mV V
76
Voste32
TE
0.3
3.3
V
12
RF SIGNAL PROCESSOR
S5L1462B
ELECTRICAL CHARACTERISTICS (Continued)
No Item Symbol Input Measuring point MIRR Min. 4.5 Output Typ. Unit Max. 0.4 V
MIRROR CIRCUIT 77 Output Voltage H 78 Output Voltage L 79 80 Mirr Hold Frequency
Vmirh Vmirl
Fhold1 (DVD) Fhold2 (CD)
MIRRI=1Vpp 1kHz sine 30% AM fc = 5MHz dc=2.5V RFRPOFST=30 RFRP_FRQ=30kHz Gain_RFRP=14dB Measure the Freq. of No 65 Mirri=1Vpp 1kHz sine 30% AM fc=5MHz dc=2.5V, RFRPOFST=30 RFRP_FRQ=320kHz Gain_RFRP=14dB Mirri=1Vpp 1kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 1kHz sine 30% AM fc=500kHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 20kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 300kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=320kHz Gain_RFRP=12dB Mirri=1Vpp 1kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 1kHz sine 30% AM fc=500kHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=320kHz Gain_RFRP=14dB
MIRR
990 99
1000 100
1010 101
Hz kHz
81
RFRP Output Level 1
Vrfrp1 (DVD)
RFRP
1.0
1.15
1.30
Vpp
82
Vrfrp2 (CD)
83
RFRP Output Level 2
Vrfrp3 (DVD)
RFRP
700
850
1000
mVpp
84
Vrfrp4 (CD)
300
450
600
85
RFRP Output Variable Range
Avorfrp1
RFRP
4.5
6
7.5
dB
86
Avorfrp2
6.5
8
9.5
13
S5L1462B
RF SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
No Item Symbol Input Measuring point RFRP Min. Output Typ. 60 Unit Max. kHz
MIRROR CIRCUIT 87 RFRP Bandwidth (-3dB)
Frfrp1
88
Frfrp2
Mirri=1Vpp 60kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB Mirri=1Vpp 120kHz sine 30% AM fc=5MHz dc=2.5V RFRP_OFST=30 RFRP_FRQ=30kHz Gain_RFRP=12dB
120
14
RF SIGNAL PROCESSOR
S5L1462B
ELECTRICAL CHARACTERISTICS (Continued)
No Item Symbol Input Measuring point Min.
4.5 0.4 DFCT DFTP_TH =300mV DFT_TH =100mV 5.0 0.5 Vpp 1.0 kHz
Output Typ. Max.
Unit
DEFECT DETECT CIRCUIT 89 90 91 92 93 Output Voltage H Output Voltage L Min Operation Frequency Max Operation Frequency Minimum Input Operation Voltage Maximum Input Operation Voltage High Speed Peak Hold Time Constant Range Vdefh Vdefl Fdef1 Fdef2 Vdefin1 (A-D)DVD1=1kHz 250mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 (A-D)DVD1=1kHz 250mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 (A-D)DVD1=1kHz 250mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 (A-D)DVD1=5kHz 250mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 (A-D)DVD1=5kHz 150mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 (A-D)DVD1=5kHz 600mVpp+Vc Gain_ABCD=0dB ABCDOFST=80 (A-D)DVD1: 250mVpp+Vc Square 5kHz Gain_ABCD=0dB DFCT_CNST=5.6us/V (A-D)DVD1: 250mVpp+Vc Square 5kHz Gain_ABCD=0dB DFCT_CNST=60us/V (A-D)DVD1=250mVpp 1kHz Sine wave, GAIN_ABCD=0dB FOK_TH=80 (A-D)DVD1=250mVpp 45kHz GAIN_ABCD=0dB, FOK_TH=80 FOKB 45K FOKB 4.5 0.4 Hz V
94
Vdefin2
1.8
95
Tphr1
5.7
us/V
96
Tphr2
60
FOK DETECT CIRCUIT 97 98 99 Output Voltage H Output Voltage L Maximum Operation Frequency Output Voltage Output Voltage H Output Voltage L Output Voltage H Output Voltage L Input PD Voltage Vfokh Vfokl Ffok V
RF ENVELOPE AMP 100 101 102 103 104 105 Venv Valpch1 Valpcl1 Valpch2 Valpcl3 Vinpd ABCDI : 2Vpp,Sine 1MHz PDdvd: +600V LDONB=1 PDdvd: +0V LDONB=1 PDcd: +600mV LDONB=1 PDcd: +0mV LDONB=1 PDdvd: DC Sweep LDONB=1 PD Value When LDdvd: 3.5V ENV (LDO) dvd (LDO) dvd (LDO) cd (LDO) cd LDO dvd 158 178 4.5 0.5 198 mV 1.66 4.5 0.5 V 1.86 2.06 V V ALPC CIRCUIT
15
S5L1462B
RF SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
No Item Symbol Input Measuring point Min. Output Typ. Max. Unit
INTERRUPT DETECT CIRCUIT 106 Output Voltage1 H 107 Output Voltage1 L 108 Output Voltage2 H 109 Output Voltage2 L 110 Minimum Operation Frequency 1 Maximum Operation Frequency 1 Minimum Operation Frequency 2 Maximum Operation Frequency 2 Minimum Input Operation Frequency Vinth1 INTERI=1Vpp 1kHz INTER_TH=80 Gain_INT=3.5dB INT_SEL=1, INT_ONB=0 (A-D)DVD1=1kHz, 250mVpp+Vc, DVD mode Gain_ABCD:6dB INTER_TH=80 Gain_INT=3.5dB, INT_SEL=0, INT_ONB=0 INTERI=1Vpp, 1kHz INTER_TH=80 Gain_INT=3.5dB INT_SEL=1, INT_ONB=0 INTERI=1Vpp, 5kHz INTER_TH=80 Gain_INT=3.5dB INT_SEL=1, INT_ONB=0 (A-D)DVD1=1kHz, 250mVpp+Vc, DVD mode INTER_TH=80, Gain_INT=3.5dB INT_SEL=0, INT_ONB=0 (A-D)DVD1=5kHz, 250mVpp+Vc, DVD mode INTER_TH=80, Gain_INT=3.5dB INT_SEL=0, INT_ONB=0 INTERI=0.5Vpp, 5kHz Pulse Symmrtry=90%, INTER_TH=80 Gain_INT=9.5dB, INT_SEL=1, INT_ONB=0 INTERI=1.8Vpp, 5kHz Pulse Symmrtry=90%, INTER_TH=80 Gain_INT=3.5dB, INT_SEL=1, INT_ONB=0 INTERO INTERO INTERO INTERO 4.5 INTERO 4.5 V
Vintl1 Vinth2
0.4 V
Vintl2 Fint11
0.4 1.0 kHz
111
Fint21
5.0
112
Fint12
1.0
kHz
113
Fint22
5.0
114
Vintin1
0.5
Vpp
115 Maximum Input Operation Frequency
Vintin2
1.8
Frequency = Fin1,DUTY=25% INPUT1 INPUT2 Frequency = Fin1*2,DUTY=50% 300mVpp 300mVpp
16
RF SIGNAL PROCESSOR
S5L1462B
SERIAL INTERFACE
* * The serial interface controls the disc type, speed, AGC, and the on/off of the laser diode. The serial interface's timing diagram is as follows.
STB DATA CLOCK A7 A0 D7 D0 Address, 8-bit Data, 8-bit
Serial Port Data Transfer Format
*
CLOCK : Clock synchronous to the data transmitted from MICOM. DATA : Address and data transmitted from MICOM. STB : Signal showing that data is enabled. Address : 00H DATA Function Initial Value D7
AGC_HOLD
D6
TE_SEL
D5
RFSUM_SEL
D4
BUF_SEL
D3
LDONB
D2
AGC_HOLD
D1 0
D0 0
SPEED_SEL
0
0
0
0
0
0
AGC1_HOLD(D7): RF AGC Peaking protection selection 0: unuse 1: use TE_SEL(D6): TRACKING ERROR selection 0: DPD RFSUM_SEL(D5): RFSUM PORT selection 0: RFSUM input 1: (A, B, C, D) input BUF_SEL(D4): Input buffer selection (RFSUM port polarity selection) 0: Buffer Bypass 1: Buffer use LDONB(D3): LASER,ON/OFF control pin 0:LASER OFF AGC1_HOLD: AGC1 peaking protection selection 0: unuse SPEED_SEL (D1 - D0) : speed selection D1 0 1 1 D0 0 0 1 MODE DVD CD CD SPEED_SEL 1X 1X 2X
1: TE3
1:LASER ON
1: use
17
S5L1462B
RF SIGNAL PROCESSOR
*
Address 01H : TRACKING BALANCE Adjustment DATA Function Initial Value 1 0 0 0 D7 D6 D5 D4 TBAL 0 0 0 0 D3 D2 D1 D0
*
3 BEAM TE: F's relative change in gain compared to E, following the value change of TBAL. TBAL 00 80 FF F GAIN +4dB 0dB -4dB
*
DPD TE: The change in the TE output voltage following the change in the TBAL value. TBAL 00 80 FF TE Output Voltage -1.2V 0V +1.2V
*
Address 02H : GAIN_RFSUM, GAIN_TE3 GAIN selection DATA Function Initial Value 0 D7 D6 D5 D4 D3 D2 D1 D0
GAIN_RFSUM 0 0 1 0 0
GAIN_TE3 1 0
*
GAIN_RFSUM (D4 - D7) : RF SUM input pin GAIN selection D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MODE (Value of RFAGCO compared to the input voltage) -6dB -4dB -2dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB -
18
RF SIGNAL PROCESSOR
S5L1462B
*
GAIN_TE3 (D0 - D3) : TE3 GAIN selection D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB -
19
S5L1462B
RF SIGNAL PROCESSOR
*
Address 03H : GAIN_FE, GAIN_ABCD GAIN selection DATA Function Initial Value 0 D7 D6 D5 D4 D3 D2 D1 GAIN_FE 0 0 0 1 1 D0
GAIN_ABCD 0 1
*
GAIN_ABCD (D4 - D7) : ABCD GAIN selection D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB 30dB
20
RF SIGNAL PROCESSOR
S5L1462B
*
GAIN_FE (D0 - D3) : FE GAIN selection D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN -2dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB
*
Address 04H - 06H : Various offset adjustment data ADDRESS 04H 05H 06H Data TE(1,3) Offset FE Offset ABCD Sum Offset Initial Value 80H 80H 80H
The output OFFSET is at its minimum at 00H, maximum at FFH, and 2.5 V at 80H.
21
S5L1462B
RF SIGNAL PROCESSOR
*
Address 07H: DPD PD LIMIT GAIN_TE1 HOLD_CTL selection
DATA Function Initial Value D7
DPD_MUTE
D6
D5 GAIN_TE1
D4
D3
D2 PD_LIMIT
D1
D0
0
0
1
0
0
0
0
0
DPD_MUTE (D7): DPD TE input pin GAIN selection 0: DPD MUTE OFF 1: DPD MUTE ON GAIN_TE1 (D4 - D6): DPD TE input pin GAIN selection D6 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 MODE (Relative value of DPDEQ1, 2 compared to the voltage) 6dB 9dB 12dB 15dB 18dB 21dB 24dB 27dB
PDLIMIT (D0 - D3): DPD PHASE DETECTOR's limit of output width D3 0 D2 0 1 1 1 1 D1 0 D0 0 Limit of Width 160ns 10ns
22
RF SIGNAL PROCESSOR
S5L1462B
*
Address 08H: Offset Adjustment ADDRESS 08H Data RFRP Offset Initial Value 80H
The output OFFSET is at its minimum at 00H, maximum at FFH, and 2.5V at 80H. * Address 0AH:
DATA Function Initial Value 1 0 0 0 D7 D6 D5 D4 D3 EQ_FREQ 0 0 0 0 D2 D1 D0
EQ_FREQ (D0 - D7): EQ frequency characteristic's minute adjustment selection EQ_FREQ 22 80 DB Amount of PEAK frequency change +60% 0% -60%
23
S5L1462B
RF SIGNAL PROCESSOR
*
Address 0BH : DATA Function Initial Value D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
EQ_BOOST
ga-Mux-TE
EQG_CEN
EQ_BOOST(D4 - D7) : GAIN minute adjustment selection from the EQ_BOOST GAIN chosen by EQG_CEN D7 0 D6 0 0 1 1 1 0 0 1 1 0 0 1 0 0 1 0 1 D5 1 D4 0 CENTER GAIN change in width -4dB -0.5dB 0dB +0.5dB 4dB
ga-Mux-TE(D2 - D3) : TE output gain control D3 D2 0 0 0 1 1 0 1 1
CENTER_BOOST GAIN 10dB 12dB 14dB 16dB
EQG_CEN(D0 - D1) : EQ_BOOST GAIN's CENTER GAIN minute adjustment selection D1 D0 CENTER_BOOST GAIN 0 0 3dB 0 1 5dB 1 0 7dB 1 1 9dB * Address 0CH : DATA Function Initial Value D7 D6 D5 D4 D3 D2 D1
SW-CON 0 0
D0
SW_CON1 0
RFRP_FRQ 0 0
GAIN_RFRP 0 0 0
RFRP-LPF
RFRP_FRQ (D6 - D7) : RFRP's PEAK-BOTTOM HOLD circuit output frequency, LPF frequency selection D7 0 0 1 1 D6 0 1 0 1 RFRP FREQ. 30 kHz 80 kHz 160 kHz 320 kHz RFRP LPF fc 60 kHz 160 kHz 320 kHz 640 kHz
24
RF SIGNAL PROCESSOR
S5L1462B
GAIN_RFRP (D4 - D5) : RFRP's output GAIN selection D5 0 0 1 1 D4 0 1 0 1 GAIN_RFRP 6dB 9.5dB 12dB 14dB
RFRP_LPF (D3 - D2): RFRP's output gain selection D3 0 0 1 1 D2 0 1 0 1 RFRP_LPF 60kHz 80kHz 100kHz 120kHz
SW_CON (D1): Defect signal selection when RF AGC/AGC1 peaking protection selection 0: Un use 1: use SW_CON1 (D0): Cpeak signal selection when RF AGC/AGC1 peaking protection selection 0: unuse 1: use * Address 0DH DATA Function Initial Value D7 0 D6 1 D5 0 D4 DFTP_TH 0 0 0 D3 D2 D1 DFT_TH 0 0 D0
AGC_LVL
AGC_LVL(D6 - D7) : RFAGC LEVEL selection D7 0 0 1 1 D6 0 1 0 1 AGC LEVEL 3.25V 3.5V 3.75V 4.0V Output Vpp 0.50Vpp 0.75Vpp 1.00Vpp 1.25Vpp
DFTP_TH(D3 - D5) : PLL DEFECT SLICE LEVEL selection D5 0 0 0 0 1 1 1 D4 0 0 1 1 0 0 1 D3 0 1 0 1 0 1 0 SLICE LEVEL 300mV 400mV 500mV 600mV 700mV 800mV 900mV
25
S5L1462B
RF SIGNAL PROCESSOR
1
1
1
1000mV
26
RF SIGNAL PROCESSOR
S5L1462B
DFT_TH(D0 - D2) : DEFECT SLICE LEVEL selection D2 0 0 0 0 1 1 1 1 * D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 SLICE LEVEL 100mV 200mV 300mV 400mV 500mV 600mV 700mV 800mV
Address 0EH: Interrupt Threshold Level selection DATA Function Initial Value D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
INTER_TH
Interrupt Level selection by the 8-Bit DAC * Address 0FH :FOK Threshold LEVEL selection DATA Function Initial Value D7 1 D6 0 D5 0 D4 FOK_TH 0 0 0 0 0 D3 D2 D1 D0
FOKB Level selection by the 8-Bit DAC
27
S5L1462B
RF SIGNAL PROCESSOR
*
Address 10H DATA Function Initial Value D7 INT_ONB 0 D6 FLT_CTL 0 D5 0 D4 0 D3 LD_SEL 0 D2 INT_SEL 0 D1 0 D0 0
DFCT_CNST
AGC1_LVL
AGC1_LVL(D0 - D1) : AGC1 output LEVEL adjustment selection D1 0 0 1 1 D0 0 1 0 1 AGC1_LVL 2.9V 3.0V 3.1V Output LEVEL 0.7V 1.0V 1.4V -
INT_SEL (D2): Interruption input selection 0: Internal input 1: External input LD_SEL(D3) : LD output selection 0 : Select LDDVD 1 : Select LDCD DFCT_CNST(D4 - D5) : PEAK HOLD time constant selection for deciding the DEFECT circuit's DEFECT minimum detection width D5 0 0 1 1 FLT_CTL(D6) : Fault out output selection. 0: Fault out output ON 1: Fault out output OFF INT_ONB(D7) : Interruption on/off selection. 0 : Interrupt Detect ON 1 : Interrupt Detect OFF D4 0 1 0 1 DEFECT 60us/V 25us/V 12.5us/V 5.6us/V
28
RF SIGNAL PROCESSOR
S5L1462B
*
Address 11H DATA Function Initial Value D7
RVSN 0
D6
Vdc25_sel 0
D5
VBGO_ SEL 0
D4
DVCTL_ SEL 0
D3
Vdc125_ sel 0
D2
AGC1_ON 0
D1
D0
GAIN_INT
0
0
GAIN_INT(D0 - D1) : Interruption GAIN adjustment selection D1 0 0 1 1 D0 0 1 0 1 GAIN 3.5dB 6dB 9.5dB 12dB Drainage X1.5 X2 X3 X4
AGC1_ON (D2) : AGC1 BLOCK ON/OFF adjustment selection 0 : AGC1 ON 1 : AGC1 OFF Vdc125_sel (D3): 1.25V reference voltage selection 0: Bandgap voltage use 1: Reference voltage use DVCTL_SEL (D4): TE1 input selection 0: (A+B), (B+D) 1: (A+D), (C+D) VBGO_SEL (D5): ALPC reference voltage input selection 0: Internal bandgap reference voltage 1: External voltage vdc25_sel (D6): 2.5V reference voltage selection 0: Bandgap voltage 1: Reference voltage
29
S5L1462B
RF SIGNAL PROCESSOR
BLOCK DESCRIPTION
RF MULTIPLEXER
BUF_SEL
RFSUM_SEL
RFSUM ADVD BDVD RFP1 RFP2
CDVD
RFP3
DDVD
RFP4 VREFO RF MUX
*
The RF Multiplexer is a block that inputs into the RF SUM AMP the I/V signals which are output differently according to each pickup, in order to get the RF AUM signal. The RFSUM generates RF signals by compensating according to the I/V polarity using the ADDRESS 00H's BUF_SEL. The RF MUX's operation is selected by ADDRESS 00H's RFSUM_SEL REGISTER, and the RF MUX output value for each RFSUM_SEL are as follows.
RFSUM_SEL (D3): Inputs and selects RFSUUM AMP's operation mode by Address 00H's (D5). (ABCD MUX & RFSUM) D3 0 1 RFP1 RFSUM ADVD RFP2 VREFO BDVD RFP3 VREFO CDVD RFP4 VREFO DDVD
30
RF SIGNAL PROCESSOR
S5L1462B
RF SUM & AGC AMP BLOCK
GAIN_RFSUM RFP1 RFP2 RFP3 RFP4
+ + RF SUM + AGC AMP + + -
RFAGCO
EQIN VCC
AGCB
-
BOTTOM PEAK AGCP
AGCC
SW
COMP
+
+
Control on/off GND
AGC_LVL
GND
*
The RF SUM AMP either adds or subtracts the input signal selected in the RF Multiplexer by the RFSUM_SEL and compensates according to the I/V polarity using ADDRESS 00H's BUF_SEL, to produce the RF signal. Also, the RF SUM AMP is able to adjust the LEVEL by the gain selected by GAIN_RFSUM (-6 - -16dB). The RF AGC circuit makes the signal whose gain was adjusted by the RFSUM AMP into a regular size. The AGC circuit's output size is selected according to the value of AGC_LVL (3.2V - 3.75V), between 0.5Vpp -1.25Vpp in increments of 0.25Vpp STEP. The AGC's response time constant is decided by the resistance capacity of the Capacitor connected to the external connection PIN (AGCP, AGCB, AGCC). SW is prohibited the peaking by hold the AGC voltage when meet the defect or interruption
*
*
31
S5L1462B
RF SIGNAL PROCESSOR
RF EQUALIZER
RFEQ_SEL EQ_FREQ
EQ_BOOST EQG_CEN
RF Equalizer H(s)=K(S2 -A2) EQIN RFEQO
Order 9 Bessel LPF
Symmetric Zero HPF
PLLGF
from D.R EQCTL
*
The RF Equalizer receives the RF AGC AMP's output signal and corrects the gain and frequency characteristics according to disc type and speed. Our RF is used in common with the RF EQ that has similar frequency characteristics. The RF EQ has 3 independent EQ characteristics, namely that of DVD 1X, CD 1X, and CD 2X. The RF Equalizer is composed of the SYMMETRIC ZERO HPF and the 9th degree BESSEL LPF. The SYMMETRIC ZERO HPF's transmission function is: H(s) = K(S 2-A 2), and is combined with BESSEL LPF to make RF EQ characteristics. The RF EQ has predetermined frequency characteristics according to disc type and speed mode. The minute adjustments of frequency and BOOST gain are carried out by Add 0CH's EQ_FREQ and Add 0BH's EQ_BOOST and EQG_CEN. The gain adjustment of the Peaking frequency is carried out by the combination of GAIN (3-9dB, 2dB/STEP) selected by EQG_CEN, and GAIN (-4.0-+4.0dB, 0.5dB/STEP) selected by EQ_BOOST. The selection of the Peaking frequency is made by the EQ_FREQ. Of the RF EQ characteristics from SPEED_SEL selection, the characteristics when EQ_FREQ=0%, EQG_CEN=5dB, and EQ_BOOST=+1dB have been shown below.
*
*
*
32
RF SIGNAL PROCESSOR
S5L1462B
Gain GPEAK EQ Range
F PEAK Characteristics of RF EQ
Frequency
EQ_FREQ=0%, EQG_CEN=7dB, EQ_BOOST=0dB SPPED_SEL 00 10 11 RF EQ RF EQ1 RF EQ2 RF EQ3 FPEAK 6.4MHz 1.3MHz 2.6MHz GPEAK +7dB +7dB +7dB
The RF EQ's PEAK frequency is the same as shown in the above RF EQ characteristics. It is therefore able to adjust to the optimal EQ characteristics demanded by the SYSTEM by EQ_FREQ's minute tuning.
33
S5L1462B
RF SIGNAL PROCESSOR
DPD TRACKING ERROR AMP
DPDEQ1 SPEED_SEL PLLCTL GAIN_TE1 + GCA + EQ comp
VCPS
DPD_MUTE PD_LIMIT
INTERO PDMIMITRES
ADVD BDVD TE1
TBAL
Phase Detecter
LPF DPDTE to MUX5
CDVD DDVD
Front Mux
+ GCA +
EQ
comp
Abnormal Waveform Detection Circuit
TE1OFST
FLT_CTL HOLD_CTL DPD TE BLOCK TE1RES GND
FAULTO DPDEQ2
*
The (A-D)DVD signal's gain is adjusted in the DPD input GAIN adjustment block by the gain selected by Address 07H's GAIN_TE1 register. The signal is then compensated in the DPD EQUALIZER and input into the COMPARATOR. The signal by passing through the COMPARATOR circuit is then adjusted for tracking balance by the VCPS (Voltage Controlled Phase Shift) circuit, whose Delay Time is adjusted by Address 01H's register TBAL. The signal, after passing through the VCPS circuit, detects the phase difference between two signals through the phase detector. The maximum width of the phase detector's output is limited by the output width limit set by Add 07H's PD_LIMIT register. The abnormal waveform detection circuit compensates for a small or unstable input signal. It executes mute when an abnormal waveform is detected, and turns the detection/compensation On or Off. The following are qualified as abnormal waveforms: When the A+C COMPARATOR output is maintained for longer than 16T. When the - B+D COMPARATOR output is maintained for longer than 16T When the output of the abnormal waveform detection circuit goes "H". When the output of the abnormal waveform detection circuit goes 'H', then goes back to "L" at the next RISING or FALLING EDGE.
* *
*
* * *
The output of the phase detector is output through the low pass filter. It is input into the MUX5 then output to the TE block. The DPD TE OFFSET is a function to correct the circuit OFFSET after phase comparison. It eliminates any OFFSET existing within the LPF block. The DPD MUTE mutes the DPD TE while correcting the DPD Offset. Mute is carried out when Add 07H's DPD_MUTE register is "H", the external DPDMUTE block's input voltage is "H", and the INTERRUPT output is "H". When TE_SEL is not in DPD MODE, the DPD BLOCK's power is turned off.
*
34
RF SIGNAL PROCESSOR
S5L1462B
3B TE AMP AND TE OUTPUT SELECTION
E F
GCA
+ -
GAIN_TE3 TEOFST TE3B TEDPD
TE_SEL M U X ga_Mux_TE LPF
10dB 16dB
TE
TBAL
* *
Tracking Balance is carried out in the following manner. The GAIN of the F signaling AMP is adjusted by the T_BAL (Tracking Balance) so that the AC level of the E, F signal input becomes the same. After the BALANCE has been adjusted, the E,F signal is operated on in the 3-Beam Tracking Error Amp by TE = k (E-F). Then the GAIN is compensated by Address 02H's GAIN_TE3 from 6dB - 20dB to compensate for the difference in disc reflectivity according to disc type. The OFFSET is compensated by TE0FST, and the signal is output as a TE3B signal. The TE3B signal is output when the TE_SEL selects either the DPD TE or the 3B TE output. The MUX TE output signal is output through the LPF (fc=20.4kHz) and the 10dB Amp. The Servo Control voltage output is compatible with the 3.3V Supply.
* * *
FOCUS ERROR AMP
A C INV AMP +
GAIN_FE FEOFST LPF INV AMP FE
B D
VC
*
The (A+C), (B+D) input signal is operated on in the FOCUS Error Amp by FE = -k((A+C)-(B+D)). The gain is compensated by Address 03H's FE_GAIN from -2dB - +28dB to account for the difference in disc reflectivity according to disc type. When the OFFSET is adjusted by FEOFST, the signal is output as an FE signal after passing through the LPF (fc=34.7kHz) and the Inversion AMP. The output is a Servo Control voltage and is compatible with the 3.3V Supply.
*
35
S5L1462B
RF SIGNAL PROCESSOR
ABCD SUM AMP
A C B D + INV AMP
GAIN_ABCD 15dB ABCD
ABCD_OFST
*
The input signals A, B, C, D are operated as ABCD = A+B+C+D in the ABCD SUM Amp. The gain is compensated by Address 03H's GAIN_ABCD from 0dB - +30dB to account for the difference in disc reflectivity according to disc type. The OFFSET is adjusted by the BACDOFST, then the signal is output as ABCD. The frequency characteristics of the output AMP are fc = 4MHz when in CD 2x mode, and fc=10MHz in DVD mode.
*
FOK DETECT CIRCUIT
ABCD ABCDI
+ FOK_TH COMP + FOKB
* *
This circuit generates the FOCUS OK signal for the SERVO. It consists of a circuit that detects the PEAK of the ABCD SUM signal, and the circuit that outputs the FOKB signal. It compares and outputs the ABCD SUM signal's output signal and the comparison LEVEL(FOK_TH).
36
RF SIGNAL PROCESSOR
S5L1462B
MIRROR CIRCUIT
VCC RFRP_FRQ CB1 BOTTOM MIRRI PEAK CP1 GAIN_RFRP RFRP_OFST GND RFRP GND GCA + LPF PEAK CP2 RFCT + COMP MIRR
* *
The RFRP circuit is a block that detects signals crossing the TRACK. The circuit receives AC-COUPLED RFAGCO signals and calculates the difference between two signals through the PEAK HOLD and BOTTOM HOLD. The response time constant of the PEAK HOLD and BOTTOM HOLD is set by Add 0CH's RFRP_FRQ, and the standard CAPACITOR value is set by the CP1 block and CAPACITOR connected to the CB1 block. (Standard value: 100pF) The AMP that produces the RFRP signal by calculating the PEAK HOLD output and the BOTTOM HOLD output receives the RFRP_OFST, and corrects the difference in DC value in the PEAK HOLD output and BOTTOM HOLD output to guarantee a DYNAMIC RANGE and adjust the gain by GAIN_RFRP from 0dB-12dB. The RFRP signal is output through the R, C 1st LPF, and the LPF's BW is decided by Address 0CH's RFRP_FRQ value. The CENTER voltage of the two signals that passed through the PEAK HOLD and BOTTOM HOLD is output to the RFCT block. The response time constant of the PEAK HOLD and BOTTOM HOLD is decided by the CAPACITOR value and resistance connected to CP2 and CB2. The MIRR signal is found by comparing the RFCT and RFRP signal, and the polarity is HIGH in the MIRROR while LOW in the PIT. Also, the amount of HYSTERISIS can be adjusted by inserting resistance between the RFCT and MIRR.
*
* *
*
37
S5L1462B
RF SIGNAL PROCESSOR
RF ENVELOPE CIRCUIT
VCC
ENVB BOTTOM ABCDI PEAK ENVP 3.5dB +
LEVEL SHIFT
ENV
GND
* * * * *
This circuit detects the RF ENVELOPE RF signal's ENVELOPE. It has the ENVELOPE detection output for adjusting the SERVO's FOCUS BIAS. The PEAK HOLD and BOTTOM HOLD's response time constant is decided by the CAPACITOR value connected to the external block ENVP, ENVB, and the standard response frequency is 10 kHz (when C = 0.01uF). The LEVEL SHIFT circuit is to make sure ENVOUT starts near 0Volts instead of at Vc LEVEL when there is no RF signal. During Focus Un-locking, the circuit outputs to the ENV output block after 3.5dB GAIN UP. The ENV signal is output to the ENV output block during Focus Un-locking after 3.5dB GAIN UP.
38
RF SIGNAL PROCESSOR
S5L1462B
DEFECT DETECT CIRCUIT
GND RFRP_FRQ ABCD PEAK DFCT DFCT_CP2 GND PEAK LONG DFCT_CP1 GND DFTP _TH DFT _TH CC1 CC2 COMP
+ INTERO COMP
DFCT1
DFCT2
PLLDFT
+
*
The DEFECT circuit detects the signal defects from damage to the reflective surface. The defects are detected in ABCD through high speed PEAK HOLD and low speed PEAK HOLD. DC is added to the high speed PEAK HOLD output, then compared with the low speed PEAK HOLD output. The high speed PEAK HOLD's response time constant is set to Add 0CH's RFRP_FRQ when a DEFECT is detected. The low speed PEAK HOLD time constant is set by the CAPACITOR connected to the RFRP_FRQ and CB_DFT block. The rate of change is same for high and low speed PEAK HOLD. The DEFECT detecting level for SERVO is set by Add 0DH's DFT_TH, and the DEFECT detecting level for PLL is set by DFTP_TH. The output of the SERVO's DEFECT is ORING with the INTERRUPT output.
*
*
INTERRUPT DEFECT CIRCUIT
INTERI
+ VREFA GAIN_INT GND VREFA INT_ONB INTER_ TH COMP + INTERO
*
The Interrupt DEFECT circuit detects signal defects from insulation layer damage during CD/DVD Mode operation. The ABCDSUM output passes through the external LPF, is amplified by the AMP, then comparatively output with the Comparator's standard voltage (INTER_TH). The AMP's GAIN is adjusted by the GAIN_INT, and this interrupt signal's use is determined by INT_ONB.
39
S5L1462B
RF SIGNAL PROCESSOR
ALPC CIRCUIT
VCC LD_SEL VCC MUX
+
PDDVD + VBGO 20k
+ -
LDODVD PICK-UP
+
3.5k GND LD_SEL PDCD 20k + VCC MUX VCC LDOCD
GND
+
PICK-UP 3.5k GND
+
GND
*
This circuit is for controlling the Laser Diode's amount of light. It sets the amount of light that is output during playback, and stabilizes it by detecting the fluctuation in Laser Power for voltage or temperature change using the Monitor Photo Diode's output current change. ALPC for CD and DVD are separate. ALPC circuit selection and On/Off are controlled by Add 00H's LDONB. The unselected ALPC maintains Off status. The ALPC reacts to the P-SUB LASER DIODE. Its standard voltage can be changed by the value of the external ZENER DIODE connected to the VREFLP_BGI block. PD's standard input voltage range is 100mV -- 0.5V.
* * *
40
RF SIGNAL PROCESSOR
S5L1462B
TEST CIRCUIT
DPDVCC
Electrolytic INTERO BNC FAULTOUT VREFDPD
DPDGND
RESET STB CLOCK DATA RFRP Cpeak RFCT
INTERI PLLDFT DFCT1
DPDEQ2
DPDEQ1
PLLCTL
MIRR
C100 R100
R11 BNC AGC1C AGC1O RFEQO BNC RFAGCO AGCC AGCBO MIRRI C15 C16 C14 R9 R8 R7 R6 CP1 CB1 RFRP CP2 CB2 RFCT RESET STB CLOCK DATA PDLIMITRES VREFDPD DPDGND TE1RES PLLCTL FAULTOUT DPDEQ2 DPDEQ1 MIRR DPDVCC INTERO INTERI AGC1IN BNC EQIN 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PLLDFT DFCT1
SW3 C12
R6 : 12K R7 : 12K R8 : 27K R9 : 33K R10 : 100K R11 : 100K C16 : 100p R12 : 1K C100: 104
C12 : 100n (104) C13 : 50n C14 : 50n C15 : 0.1u
DVCC Electrolytic DGND DFCT_CP DFCT_CP1 FOKB ENV BNC ABCDI ABCD VREFA1 TE
C17 SW4 SW5 C19 C20 R15 C22 R13 R14
C21 R12 VZOCTL PLLGF C17 : 0.01u C18 : 0.1u C19 : 0.47u C20 : 0.01u C21 : 0.01u C22 : 0.01u
VREFLP_BGI
ADVD BDVD CDVD DDVD RREFBF RREFEQ RREF VREFEQ ADVD1 BDVD1 CDVD1 DDVD1 AVCC VREFA E F
R12 : 100k R13 : 100k R14 : 5k R15 : 20K
RFSUM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 C1 C2 C3 C4 C5 R1 R2 R3
LDODVD PDDVD LDOCD PDCD AGND FE
MIRRI EQVCC AGC1O AGC1C AGC1IN RFEQO EQIN RFAGCO AGCC EQGND AGCBO AGCB AGCP RDPF VZOCTL PLLGF
S5L1462B
DVCC CC2 CC1 DFCT_CP DFCT_CP1 FOKB DGND ENV ENVB ENVP ABCDI ABCD VREFA1 AVCC1 TE CE
40 39 C11 38 37 C10 C9 36 35 34 33 32 C8 31 C7 30 29 28 27 26 25 C6_1
R4 SW2
EQVGND
EQVCC
C1: 224 C2 - C5: 0.1u ABCD R1: 12K SW1 R2: 12K R3: 12K BNC BNC BNC RFSUM A B
BNC
Electrolytic VREFA
VFEFPL_ BGI LD PD FE
C6_1:102 C6 :103 C7 :473 C8 :473 C9 :224 C10 :100p C11 :224 R4 :100k R5 :100k AGND Electrolytic Cap AVCC
Electrolytic
Electrolytic
EF
BNC
41
S5L1462B
RF SIGNAL PROCESSOR
PACKAGE DIMENSION
23.90 + 0.30 20.00 0-8
+ 0.10
0.15 - 0.05
+ 0.30
14.00
17.90
0.10 MAX (1.00)
#1 0.80
0.35 +
0.10
0.15 MAX
0.05 MIN (0.80) 2.65 +
0.10
3.00 MAX
0.80 + 0.20
NOTE: Dimensions are in millimeters.
42
0.80
#80
+ 0.20
RF SIGNAL PROCESSOR
S5L1462B
NOTES
43

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